GUC finalizes HBM4E IP design for TSMC’s N2P processMachine translation
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GUC announced that its HBM4E PHY and controller IP for TSMC’s N2P process has been finalized and adopted for a customer AI ASIC. The IP supports 16Gbps data transfer and CoWoS-S/R/L packaging. A face-up version for 3D SoIC integrates TSVs for vertical signal and power transmission.
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