Article · AI translation
IT Home reported on November 11 that Huawei Kirin’s official WeChat account published an article today detailing the new-generation Da Vinci architecture NPU in the Kirin 9050 series, the first τ chip to use “logic folding” technology. It supports running 30B-parameter large models on-device, without needing an internet connection or waiting for the cloud.
The new-generation Da Vinci architecture NPU delivers a 140% performance improvement and 66% lower power consumption, and supports a Transformer engine, an ultra-low-power sensing engine, and the CANN heterogeneous computing architecture. It brings what is described as the industry’s first 30B MoE large model to the device, with support for multilevel collaborative optimization of storage and computing and low-bit quantization.
In terms of specific features, the new-generation Da Vinci architecture NPU can provide screen sensing for AI screen reading, image sensing for Xmage Smart Capture 2.0, eye sensing for AI eye-movement page turning, and location sensing for Screen-Off Maps 2.0.
As IT Home previously reported, at Huawei’s 2026 Kirin media briefing held in October this year, Xu Songyu, head of product management for wireless terminal chips in Huawei’s semiconductor business, said that the Kirin 9050 series, as the first logic-folded τ chip, would embark on a new journey for the next 10 years. A presentation slide showed that Huawei aims to push P-core frequencies beyond 5GHz by 2031.