正文 · AI 翻译
What takes a GPU 100 iterations, it does in one step
Keleixi reporting from Aofei Temple
QbitAI | WeChat public account QbitAI
Keleixi reporting from Aofei Temple
QbitAI | WeChat public account QbitAI
Analog computing, which humanity has used for 2,000 years, is beginning to be redefined.
In a Nature-affiliated journal devoted to unconventional computing, a review paper puts “modern analog computing” in its title, seeking to establish a formal definition for the field.
The effort was led by Sun Zhong, a tenured associate professor at Peking University’s Institute for Artificial Intelligence, who is also slated to become chief scientist of analog computing chip company AnnazhiXin.
The 4 authors, including Sun Zhong, come from Peking University, IBM Research Zurich and Silicon Valley startup Unconventional AI, bringing together nearly all of the leading forces in analog computing today.
From left: Shahar Kvatinsky (IEEE Fellow), Sun Zhong, Abu Sebastian (IEEE Fellow), Piergiulio Mannocci
IBM has worked in analog computing and computing in memory for more than 10 years and is widely regarded as a benchmark in the field. Review coauthors Manuel Le Gallo and Abu Sebastian are researchers at IBM Research Zurich; Sebastian is also an IEEE Fellow and a longtime leading researcher in this area.
Meanwhile, investors are scrambling for Silicon Valley analog computing companies. Unconventional AI’s valuation has exceeded $4.5 billion, and Normal Computing has secured investment from Samsung and Eric Schmidt. Both companies claim they “can reduce AI energy consumption to one-thousandth.”
Sun Zhong has long tried to bring coherence to a field. He did the same in computing in memory 2 or 3 years ago, joining international colleagues to write a paper titled “A full spectrum of computing-in-memory technologies,” published in Nature Electronics.
He said the paper was just an opportunity: he wanted to bring together several of the most important institutions in China and abroad to jointly write a definition of “modern analog computing.”
How to define “modern analog computing”
In this review paper, refined over several years, the 4 authors make the word “modern” the pivot of their entire framework.
For many people, the first thing that comes to mind when they hear analog computing is the old machines displaced by digital chips half a century ago.
To clarify the concept, the paper distinguishes “modern analog computing” from “traditional analog computing” along 3 dimensions.
In terms of tasks, traditional analog computing addressed only differential equations, while modern analog computing primarily addresses the matrix computations in greatest demand in the AI era and 6G communications.
In terms of hardware, traditional analog computing relied on CMOS analog circuits, while modern analog computing is rooted in new nanoscale devices such as resistive random-access memory (RRAM and other memristors).
In terms of practical application, traditional analog computing was held back by low precision and difficulty scaling. Modern analog computing has explored engineering paths to high precision and scalability, and uses a rigorous framework to define its boundaries, primitives and path of development.
Understanding this new framework requires a fresh understanding of the word “analog.”
To many people educated in modern engineering, digital computing means “discrete,” while analog computing is simply assumed to mean “continuous.”
In his presentation, Sun Zhong cited research by scholar Corey J. Maley published in WIREs Cognitive Science in 2024.
That research argues that the core concept of “analog” is not continuity but “analogy”: mapping a mathematical problem directly onto a physical system without abstracting it into binary symbols, and relying on physical laws to produce the answer naturally.
Everyday experience is full of examples of analog computing.
When children learn arithmetic, 1 apple plus 1 apple equals 2 apples; to multiply 3×5, they put together 3 piles of 5 apples and count 15. These are the most direct physical mappings.
Analog computing chips use the same kind of analogy, seeking physical entities in microscopic circuits that correspond to mathematical variables.
But doing this in conventional integrated circuits presents obstacles.
The physical quantities in a circuit that can usually change in real time are voltage and current, while the resistance of an on-chip resistor is fixed once it has been manufactured.
To use Ohm’s law for multiplication, both factors keep changing. One number can be supplied as a voltage signal, but if the other is represented by a fixed resistor, the circuit cannot handle dynamic computing tasks.
The key to overcoming this input constraint is finding a physical medium in the circuit whose value can be rewritten at any time and retained for a long time.
Resistive random-access memory, often called a memristor, offers precisely that possibility. The defining property of this new nanoscale device is that its conductivity is not fixed: it can be changed precisely by applying electrical pulses, and its resistance is retained after power is turned off.
In effect, this gives integrated circuits a new physical variable beyond voltage and current: “conductance,” which can be stored in place and adjusted at any time.
The 2 input numbers in a multiplication therefore each have a physical counterpart in the circuit: 1 is programmed directly as the device’s conductance, and the other is applied as a voltage across it.
At the instant current flows, Ohm’s law makes the magnitude of the output current the product of the 2.
When voltages applied to each row drive the devices to generate multiple currents that flow into the same column wire, physical laws again perform the computation. Under Kirchhoff’s current law, the total current flowing into a node must equal the sum of the currents in its branches, so parallel currents naturally combine and add.
This means Ohm’s law handles each multiplication and Kirchhoff’s law handles the summation: the multiply-accumulate results for an entire column are calculated at once as the currents merge in the wire.
With peripheral operational amplifiers forming a closed feedback loop, modern analog computing chips can also solve equations.
Through negative feedback, a powered circuit spontaneously converges to a physical equilibrium within nanoseconds, and the stable voltage at that equilibrium is mathematically the solution to the equation.
Beyond the limited physical variables available, traditional analog computing faced another critical bottleneck: it could not scale up.
In earlier designs based on CMOS operational-amplifier circuits, each operator required many transistors, making area efficiency extremely poor.
A 65-nanometer CMOS analog chip described in a 2016 paper in the leading integrated-circuits journal JSSC occupied a substantial area yet could hold only 4 integrators and 8 multipliers.
Moreover, analog voltage signals degrade severely when transmitted long distances through a circuit, and CMOS operational amplifiers occupy considerable area. Integrating 1 million CMOS multipliers on a single chip is almost physically infeasible.
New memory devices have broken through that barrier. A miniature 1000×1000 resistive-memory crossbar array can now compactly integrate 1 million inherent multipliers at high density.
Modern analog computing broke the scalability deadlock by replacing complex CMOS analog units with new resistive-memory devices.
A resistive device is essentially a 2-terminal nanoscale component measuring only tens of nanometers. To fabricate it, engineers need only lay out 1000 horizontal metal row wires, cross them in 3 dimensions with 1000 vertical metal column wires, and place a layer of resistive material at each microscopic crossing.
This 3-dimensional network of 1000 wires in each direction creates fully 1 million physical intersections in a tiny chip area.
Each intersection has its own conductance value. Apply voltage to a row wire and current flows from an intersection: these 1 million nanoscale intersections are inherently 1 million parallel analog multipliers operating in place.
Building on this hardware transition, the review paper groups analog computing into 3 core primitives: solving differential equations, solving matrix equations, and matrix-vector multiplication (MVM).
All 3 share the same basic operators—adders, multipliers and integrators—and are closely connected at both the mathematical and circuit levels.
A differential equation can be converted into a matrix equation through discretization. A matrix equation can either be approximated through repeated iterations of matrix multiplication or solved directly in 1 step using an analog closed-loop network. The 3 are interconnected and form a unified family of computations.
Sun Zhong said there is little novelty in using an analog circuit in isolation to solve a particular equation or perform multiplication. His reason for writing the paper was to connect these scattered techniques, establish a complete framework for modern analog computing, and define a clear direction.
What takes a GPU 100 iterations, it does in one step
Defining a new framework requires support from disruptive results measured in practice.
Many teams in the integrated-circuit industry are developing chips that combine memory and computing, but the vast majority focus on “accelerating matrix multiplication,” mainly for AI inference.
Sun Zhong and AnnazhiXin chose a more technically challenging and distinctive route, starting with solving matrix equations and matrix inversion.
Behind that choice lies one of the biggest pain points for digital chips in real-world computing.
Under the heavy workloads of AI computing centers and scientific computing, more than 80% of computing resources are often spent solving systems of linear equations of the form Ax=b.
Mathematically, solving such a system centers on finding the unknown vector x, and the difficult step of “matrix inversion” is hard to avoid.
Matrix inversion, however, is precisely the operation traditional digital chips struggle with most.
Compared with relatively simple matrix multiplication, matrix inversion has very high computational complexity, typically O(n^3).
Digital chips have no dedicated hardware unit that can directly invert a matrix. To perform an inversion, a general-purpose GPU must use numerical algorithms to break it into dozens or even hundreds of matrix multiplications, repeating them to approach the answer gradually.
As a result, vast amounts of costly computing power and time are consumed by lengthy iterative calculations and data movement.
The analog matrix computing (AMC) circuit designed by AnnazhiXin changes the rules. The team introduced a global negative-feedback closed loop around a resistive-memory array, making the circuit’s transient response correspond directly to the solution of a matrix equation.
An operation that previously required a GPU to carry out more than 100 iterations can yield an accurate solution from the AMC circuit in a single measurement. One operation takes less than 100 nanoseconds, and that physical response time does not depend on the matrix dimensions.
But however fast the computation, an analog chip cannot leave the laboratory if its answers are inaccurate. Precision has long been the Achilles’ heel of practical analog computing.
When Sun Zhong’s team demonstrated solving a matrix equation in 1 step in PNAS in 2019, fluctuations in the analog devices limited the relative error to about 3%, and the hardware array measured only 3×3.
This longstanding technical problem was not fully overcome until October 2025.
At that time, Sun Zhong’s team published a breakthrough paper in Nature Electronics proposing an approach to solving matrix equations with analog hardware that combined high precision with scalability.
Because continuous conductance states drift easily and cause inaccuracies, the team drew on the bit-slicing concept of early digital computers. They abandoned unreliable continuous states and instead used 8 thoroughly validated discrete conductance states in each device, equivalent to 3 bits.
By combining 8 array slices of 3 bits each, the system achieved 24-bit fixed-point precision.
Low-precision inversion establishes the direction, while high-precision multiplication gradually eliminates residual error. After only 3 iterations, the relative error fell to 10^-4 and could subsequently converge to 10^-7, a level matching the FP32 single-precision floating-point operations of digital processors.
Because bit slicing allows further expansion, the precision of this analog approach theoretically has no upper limit and can continue to improve by increasing the number of slices and iterations.
To tackle larger real-world problems, the team also designed BlockAMC, a block algorithm that progressively breaks a huge matrix into subblocks the hardware array can handle, performing inversion and multiplication in batches. In tests, it has successfully scaled to complex 512×512 matrices.
After addressing precision, the next engineering challenge was how to make this analog system work seamlessly with the existing digital world.
Sun Zhong and the development team knew that today’s IT infrastructure rests entirely on a digital foundation. A standalone, purely analog chip would have no commercial future; analog computing had to work alongside the digital ecosystem.
In Anna Zhixin’s chip architecture, dedicated miniature analog cores perform matrix operations. Analog-to-digital converters (ADCs) quickly turn the results into digital signals; data travels between cores and across chips through digital channels, while established digital logic handles nonlinear operations such as square roots and trigonometric functions.
The team summed up this approach as “leave matrices to analog, and logic to digital.”
For this hybrid digital-analog approach, the chip industry’s most natural concern is often the overhead at the interfaces.
Signals must be converted between digital and analog before and after each analog core, using DACs and ADCs. Would the energy consumed by frequent conversions wipe out all the energy savings from analog computing?
Looking only at energy use within the analog computing module, DACs and ADCs do indeed account for the vast majority.
But thanks to the bit-sliced architecture, each subarray processes only 3-bit data. The peripheral circuitry therefore has no need for high-specification ADCs with more than 10 bits and high sampling rates; basic converters with 6- to 8-bit resolution and a 10 MHz sampling rate suffice.
In chip design, relaxing precision and sampling-rate requirements can substantially reduce power consumption and chip area.
Thus, even after accounting for all the overhead of digital-analog conversion before and after computation, measured evaluations still show that, at FP32 precision equivalent to digital chips, this analog matrix computing approach delivers about 1000 times the throughput of a single Nvidia H100 core and a digital ASIC, and about 100 times their energy efficiency.
Beyond its advantage in computing performance, the architecture also avoids costly foundry barriers in manufacturing and supply chains.
To increase compute density, digital GPUs must keep investing in advanced extreme-ultraviolet lithography processes such as 3 nm and 2 nm, while resistive memory can already be manufactured reliably on mature 28 nm and even 22 nm processes.
Domestic wafer foundries have built up capabilities in mature resistive-device processes on par with international giants, allowing the chip to be produced with independently controlled capacity and giving it an overall cost advantage of about 10 times over mainstream GPUs.
With a foundation of 1000 times the throughput, 100 times the energy efficiency, and one-tenth the cost, the technology’s commercialization points directly to real-world applications where industry has the greatest need to solve linear equations and invert matrices.
In the near term, Anna Zhixin expects to present a tested demonstration for embodied-intelligence motion control and planning within 1 year.
When robots perform highly dynamic motion control, they must solve complex dynamics matrix equations in real time. AMC circuits’ ability to solve them in microseconds could make robot joint movements smoother and less jerky.
In the medium term, Anna Zhixin is focusing on massive MIMO signal processing in 6G wireless communications.
Wireless signal detection likewise rests on solving channel matrix equations. In massive MIMO experiments for 5G-A and 6G base stations, the Peking University team restored an image of the university emblem and a 256-QAM constellation diagram with zero errors after 3 iterations; its bit-error-rate curve overlapped with that of a digital FP32 approach.
In its longer-term plan for the next 3 to 5 years, the team aims to scale the chip to thousands of parallel analog cores to natively support second-order optimization in large-model training.
In theory, second-order optimization converges faster than traditional first-order optimization, but every step requires inverting a Hessian matrix. In the past, digital GPUs simply could not handle the computation, so model developers had to settle for an approximation using 5 iterations of matrix multiplication.
Once high-precision analog matrix inversion supported natively by hardware is put into use, the physical bottleneck in optimizing large-model training will be eased.
This time, Silicon Valley and China define it together
In semiconductors and frontier computing, people have long been accustomed to a familiar script.
Silicon Valley pioneers a new technological path, and domestic teams quickly follow.
But in modern analog computing, the script has been reversed.
The person leading a collaboration with IBM Research Zurich and a Silicon Valley unicorn to define the field and set its boundaries is Chinese scholar Sun Zhong.
In this field, the foundational paper came from his team, and he broke through the precision problem that had plagued the industry for decades;
in industry, the core approaches taken by 2 Silicon Valley stars of unconventional computing, each valued at billions of dollars, also grew out of his research.
Securing a leading position in this field, which represents the future of frontier computing, rests on strength in 2 areas.
Academically, Sun Zhong published a study in PNAS in 2019 as first author on solving matrix equations in 1 step with a resistive array. It was the field’s first foundational paper.
A 2025 Nature Electronics paper that overcame the precision bottleneck set the journal’s record for readership in its 9-year history after it went online.
The work received in-depth coverage from major media and, alongside DeepSeek, was selected as one of the “Top 10 Domestic Science and Technology News Stories of 2025.” It also won the “Top 10 Advances in Chinese Chip Science in 2025” and the “Emerging Industry Award,” was selected for the permanent exhibition and the original-innovation exhibition at the 2026 Zhongguancun Forum, and was named “Best Academic Paper” at the 2026 China Computing Power Conference.
More persuasive than academic honors is the industry following from across the Pacific.
The underlying technologies of 2 pioneering Silicon Valley computing startups backed heavily by leading investors are evolving in step with his research.
One is Normal Computing, founded by former Google Brain and Palantir team members. It taped out its thermodynamic computing chip, CN101, in 2025 and has raised more than $85 million in total. Its investors include Samsung, Eric Schmidt’s First Spark Ventures, and the UK’s Advanced Research and Invention Agency (ARIA).
In the company’s 2026 npj Unconventional Computing paper, “Thermodynamic Natural Gradient Descent,” and its subsequent work on second-order optimization, the core solving hardware is a closed-loop negative-feedback analog inversion circuit.
Sun Zhong clearly compared the 2 topologies in a presentation slide, annotating them with “Another name, same circuit” to show how closely their underlying hardware matches.
The other is Unconventional AI, founded by former Databricks AI head Naveen Rao. Its announced seed-round valuation exceeded $4.5 billion.
Piergiulio Mannocci, one of the coauthors of the “Modern Analog Computing” review paper, worked closely with Sun Zhong at Politecnico di Milano earlier in his career and is now a core researcher at Unconventional AI.
While following public talks by the Unconventional AI team, Sun Zhong noticed that its proposed unconventional analog architecture closely aligned with the academic views he had advanced for years.
The contrasting emphasis in how companies in the 2 regions promote their work is worth examining.
Silicon Valley companies tend to promote “reducing AI energy consumption to one-thousandth” as their main selling point, closely tied to the severe constraints they face from electricity-grid demand.
Domestic teams such as Anna Zhixin instead emphasize “increasing computing speed 100-fold.” With limited computing resources, China’s AI researchers have a more pressing need to shorten model training and iteration cycles.
But whether the aim is to save electricity or increase speed, both sides must ultimately clear the same make-or-break hurdle for analog chips to move from the lab into industry: precision.
As computer pioneer Richard Sutton showed in “The Bitter Lesson,” the development of analog computing over the past half-century has also involved painful lessons.
Past research often retreated to the limited value of low-precision hardware in specific fault-tolerant tasks, but attempts at industrial deployment have repeatedly shown that computing architectures lacking precision struggle to gain a foothold in mainstream industry.
High precision is therefore a prerequisite for new computing architectures to move from the lab into industry. Since the publication of the high-precision work in 2025, discussion of “high-precision analog computing” has increased markedly in international academia and industry, which are gradually converging on this practical standard.
After this review is published, “Modern Analog Computing” will enter the citation trail of subsequent research as a formal term. Its defining framework came from Peking University and bears the joint endorsement of academic and industry authors from China and abroad.
For Sun Zhong, this is only the first step.
What he wants more is that, when this field grows into an industry in the next 5 to 10 years, anyone looking back at the original defining paper will find Chinese scholars’ names on its author page.